1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. The interface in Java is a mechanism to achieve abstraction. Getting Started 3. 2 and XAUI. XGMII interface in my view will be short lived. Local fault happens, all data sent by client user logic are dropped. PMA. 49. AXI4-Lite $;, &URVVEDU ,3 AXI4-Lite 1G Ethernet GMII Interface PCS IP /LQH 5DWH 6ZLWFKLQJ /RJLF. 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto. interface is the XGMII that is defined in Clause 46. After the 10 Gbps data is extracted from the four lanes, it must be formatted in a XGMII interface. XFI and SFI electrical specifications respectively apply to XFP and SFP+ system front port optical modules. (MAC) core, which can be configured in XGMII and 10GBASE-R modes. Additional info: Design done, FPGA proven, Specification done. 3 protocol and MAC specification to an operating speedof 10 Gb/s. You may refer to the applicable IEEE802. Intel® Stratix® 10 devices offer up to 144 transceivers with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications. 25 MHz interface clock. 3. XGMII – 10 Gb/s Medium independent interface. Hardware and Software Requirements. Lane 0: xgmii_tx_control[0] Lane 1: xgmii_tx_control[1] Lane 2: xgmii_tx_control[2] Lane 3: xgmii_tx. 1. The XGMII Controller interface block interfaces with the Data rate adaptation block. TX XGMII Mapping to Standard SDR XGMII Interface The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. Configuration Registers Description x. MII Interface Signals 5. 3 standard. 25 Gbps. 10G/25G Ethernet (PCS only) RX_MII alignment. 3) enabled Pattern Gen code for continues sending of packet . 3125 Gb/s link. Interface (XGMII) 46. 2. 5M transfers/s) • PHY line rate is preserved (10. 4. Intel PRO/1000 GT PCI network interface controller. Register Access Definition 8. For more information on aggregation mode, refer to the C-5 Network Processor Architecture Guide. Maps packets between XGMII format and PMA service interface format. I have however been just a functional person and just a technical person. The data are multiplexing to 4 lanes in the physical layer. After that, the IP asserts. 25 MHz. The XgmiiSource drives XGMII traffic into a design. A DLLP packet starts with an SDP (Start of DLLP Packet -. 1 of the IEEE P802. The optional WAN Interface Sublayer (WIS) part of th e 10GBASE-R standard is not implemented in this core. This configurable core provides the complete Media Access Control (MAC) and Physical (PHY) layer when used with a transceiver interface. 1. This specification is targeted towards the requirements of embedded systems. This is the SDS (Start of Data Stream). al [11] establish a . 0 5 Network Controller Sideband Interface (NC-SI) 6 Specification 7 Document Type: Specification 8 Document Status: DMTF Standard The IEEE 802. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double datarate – DDR) of the 156. This includes not disabling Duty Cycle Correction for Virtex-II DCMs (as was done in XAPP606). 5Gb/s 8B/10B encoded - 3. 25MHz. I'm currently reading the IEEE XGMII specification (IEEE Std 802. 5. RXAUI. When TCP/IP network is applied in. Out : 4 : Control bits for each lane in xgmii_tx_data[]. 5/ commas. USXGMII Subsystem. 1: XGMII (Clause 46) - Logical o 32-bit DDR TXD, 4-bit TXC and TX_CLK o 32-bit DDR RXD, 4-bit RXC and RX_CLK XGXS (Clause 47) – XAUI Electrical Spec (PMA) o 4 SERDES TX and 4 SERDES RX (PCS 8B/10B) @ 3. The Gigabit-Ethernet media independent interface (GMII) specified by IEEE802. Loading Application. The XGMII has an optional physical instantiation. The names, trademarks and file systems used are listed in Table 1 (below). Arasan’s 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802. 3. 2) enabled TX and RX bit in TX_ctrl and Rxctrl registers . 5 volts per EIA/JESD8-6 and select from the options > within that specification. arm is only willing to license the relevant amba specification to you on condition that you accept all of the terms in this licence. Section Content Features Release Information LL. XGMII interface in my view will be short lived. 2. The XCM . 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. On the opposite side a pair of XGMII interfaces are used to transfer frames between the nfmac10g and the PCS/PMA (or XAUI) core. Code replication/removal of lower rates onto the 10GE link. 3ae-2002). Reconfiguration Signals 6. Loading Application. 3 protocol and MAC specification to an operating speedof 10 Gb/s. 3. 4. IP is needed to interface the Transceiver with the XGMII compliant MAC. Front-Light Manager. If anybody is interested to see this document please go to FC web site at and search for doc 99-251v3. 5000BASE-X, 2500BASE-X, and 1000BASE-X (SGMII) interface for connection to a MAC. Table 1. -Avalon ST TX and RX input/output signals to Avalon ST TX/RX 64 bit adapter. By offering a standard, hot swappable electrical interface, a single gigabit port can support a wide range of physical media, from copper to long-wave single-mode optical fiber, at. > > 1. Resources Developer Site; Xilinx Wiki; Xilinx Github10 Gigabit Attachment Unit Interface ( XAUI / ˈzaʊi / ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of. 3. Arasan’s 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802. If anybody is interested to see this document please go to FC web site at and search for doc 99-251v3. 3125Gbps transmission across lossy backplanes. qua si-contract-based development. 3, Clause 47. 3bz-2016 amending the XGMII specification to support operation at 2. Each direction is independent and contains a 32-bit data path, as well as clock and control signals. XGMII Mapping to Standard SDR XGMII Data 5. About LL Ethernet 10G MAC x 1. . Avalon® -MM Interface Signals 6. It also supports the 4-bit wide MII interface as defined in the IEEE 802. 5. The generic nature of this interface facilitates mapping the CoaXPress signaling into the. 5V tolerance seems an unnecessary burden. For example, if the PCS-PMA interface is 32-bit, tx_clkout and rx_clkout run at 10. General Purpose Broad Range of Applications. Between the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. GMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in. I would not want to retain the current electrical specification. 3z specification. In any case, the base concept is still the same - I don't think that your SFP module understands that it's communicating with a USXGMII core on the MAC side, which is why it's failing to complete AN and failing to get a link established. 2 V or 2. Serial Data Interface 5. CPRI Intel® FPGA IP core contains the logic for Ethernet PCS. Where possible the PIPE specification references the PCI Express base specification specification rather than repeating its content. 5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements USXGMII PCS based on Cisco specification. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. 3 の第 49 項で定義されている BASE-R PCS/PHY (Physical Coding Sublayer/Physical Layer) を採用し、10M、100M、1G、2. Reconfiguration Signals 6. Application. 7. XGMII, as defi ned in IEEE Std 802. 11. This is most critical for high density switches and PHY. • The TX state machines needs a check to prevent this from happening. The RGMII interface has been designed in accordance with the standards and specifications agreed in theThe present clauses in 802. This technology is called 10 Gigabit Ethernet Attachment Unit Interface, and is generally. 3-2018, Clause 46. WishBone compliant: Yes. 1 Overview This clause defines the logical and electrical characteristics for the Reconciliation Sublayer (RS) and 10Gigabit Media Independent Interface (XGMII) between Ethernet media access controllers and various PHYs. XGMII Signals 6. Reconfiguration Interface and Dynamic Reconfiguration 7. A gigabit interface converter ( GBIC) is a standard for transceivers, first defined in 1995 and commonly used with Gigabit Ethernet and Fibre Channel for some time. In this demo, the FiFo_wrapper_top module provides this interface. The 5GBASE-R PCS provides all services required by the XGMII including Encoding (decoding) of XGMII data octets to (from) 64B/66B blocks for communication with the underlying PMA. The host application requests this xml file from the device and creates a register tree. Fair and Open Competition. Therefore SOP occurs on 4-byte boundaries rather than 8-byte and local and remote fault encoding is slightly different from XLGMII. Similarly, the XGMII bus corresponds to 10 Gigabit network. Table 13. PHY register map Original: PDF P1394a P1394a 32-bit 64-bit 1A16 S100 EIA-364-B: 2004 - Not Available. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including:The 64b/66b encoder is used to achieve DC balance and sufficient data transitions for clock recovery. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. 125 Gbps) or XFI (1x10. AUTOSAR Introduction - Part 2 21-Jul-2021. It is obvious that significant physical and protocol differences exist between SPI4. The signal mapping is compatible with the 64b MAC. - Wishbone Interface for control. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. 5GPII Implementation as shown does not require much incremental logic Does not preclude implementations that directly map XGMII into PCS Diagram above for IEEE functional specification purposes only 1000BASE-X PHY 2. Performance and Resource. // Documentation Portal . semi-formal notation to model SoS architectures with. 5. 2 Performance 10 2. It's an attempt to realize the Open RAN concept. 10 Gigabit Attachment Unit Interface (XAUI / ˈ z aʊ i / ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802. Implements DTE XGXS, PHY XGXS, and 10GBASE-X PCS in a single single encrypted HDL. SwitchEvent. Sublayers (XGXS) to extend the reach of the XGMII for 10 Gb/s operation. 0 that is designed to support both the device family using the IOD blocks used with GPIO or HSIO buffers. 100G only has 1 data interface. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100Support to extend the IEEE 802. 4. Text: PHY devices via 10-Gbps media independent interface (XGMII) or 10-Gbps attachment unit interface (XAUI) Management data input/output. The gigabit media independent interface (GMII) allows the CPRI Intel® FPGA IP to communicate directly with an external Ethernet MAC block. 3 standard. Reference HSTL at 1. > 3. 3 designed for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). Operating Speed and Status Signals. 3 layer diagram 100Mb/s and above RS. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. 0 > 2. While the XGMII is an optional interface, it is used extensively in this standard as a basis for functional specification and provides a common service interface for Clauses 47, 48, and 49. 1. 4 PHYs defined in IEEE Std 802. • Operate in both half and full duplex and at all port speeds. > > 1. I see three alternatives that would allow us to go forward to > TF ballot. Design Example MAC Variant PHY Development Kit 10GBase-R Ethernet 10G Native PHY Intel Arria 10 GX Transceiver SI. • No internal interface is super-rated, • XGMII rate is preserved (312. 0 5 Network Controller Sideband Interface (NC-SI) 6 Specification 7 Document Type: Specification 8 Document Status: DMTF Standard 9 Document Language: EThe IEEE 802. > > 1. Return to the SSTL specifications of Draft 1. By default, the MAC TX inserts 7-byte preamble, 1-byte SFD and 1-byte EFD (0xFD) into frames received from the client. •400 Gb/s Ethernet • Support a MAC data rate of 400 Gb/s • Support a BER of better than or equal to 10^-13 at the MAC/PLS service interface (or the frame loss ratio equivalent) for 400 Gb/sBeginner. XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between. Georg Pauwen. Device Family Support 2. High-level overview. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. 1. the official core works at 1Gbps, and the MGT can be configured tow work at 2. Return to the SSTL specifications of Draft 1. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. 25MHz, DDR) XGTMII[35:0] Output XGMII Transmit Data and Control Signals. Download Core Submit Issue. Introduction. 0 > 2. 2 Features The IP core has the following features: • 64-bit XGMII interface (MAC side) • 64-bit gearbox mode (Transceiver side) • Supported for only 64B66B PCS encoding in the transceiver • Converts the gearbox signals to the XGMII signals on the transmit interface25G-MII is a speeded up version of XGMII rather than a slowed down version of XLGMII. Configuration Registers 6. RGMII, XGMII, SGMII, or USXGMII. Return to the SSTL specifications of Draft 1. e. XGMII stands for X(roman 10)-G-Media-Independant-Interface which is IEEE 802. USGMII Specification. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. See moreThe XGMII interface, specified by IEEE 802. Core10GMAC supports standard Ethernet interfaces such as the 10 Gbps attachment unit interface (XAUI) and the 10 Gbps reduced attachment unit interface (RXAUI). 1 XGMII Controller Interface 3. 4. 0, April 2015 2 LatticeECP3 and ECP5 XAUI IP Core User Guide. 2 PCIE Interface PCI Express Gen3: Single port X4 lanes Compliant with PCI Express Base Specification Rev. PMA – Physical medium attachment. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification. 15The 100G Ethernet Verification IP is compliant with IEEE 802. authors of this specification disclaim all liability, including liability for infringement of proprietary rights, relating to implementation of information in this. With the inclusion of the XAUI interface, the 10 GMAC core can now support 10. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification. On the user side a pair of AXI4-Stream (one master and one slave) interfaces are used to send and receive Ethernet frames from/to the user logic. The original single row of pins is compatible. XGMII electricals > > > > > > >In an effort to get us all on the same page, here are links to >the standard XGMII interface proposals, SSTL-2 and HSTL Class 1 >on the JEDEC site under "Free Standards":. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. 3125 Gbps serial line rate with 64B/66B encoding. 3 10 Gbps Ethernet standard. Debug Steps: 1. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. 5. 3ae specification, the 10Gb Ethernet MAC (10 GMAC) core includes the option of either a parallel 10 Gigabit Media Independent Interface (XGMII) or a serial 10 Gigabit Attachment Unit Interface (XAUI). The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. WishBone version: n/a. 5x faster (modified) 2. The TLK3134 provides high-speed bidirectional point-to-point data transmissions with up to 30 Gbps of raw data transmission capacity. Figure 4: 10GBASE-R PHY Structure. 0 - January 2010) Agenda IEEE 802. Return to the SSTL specifications of Draft 1. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture 6. PG251 October 4, 2017 Product Specification Introduction The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2. Transceiver Reconfiguration 8. 1 2 Document Number: DSP0222 3 Date: 2009-07-21 4 Version: 1. 7. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. Thanks, I have this problem too. 201. Transceiver Status and Transceiver Clock Status Signals 6. Section Content Features Release Information LL. PCS Registers 5. SD 4. 1858. As a result the above text only applies to XGMII 10 Gb/s operation and IEEE 802. IEEE 802. USGMII provides flexibility to add new features while maintaining backward compatibility. PCS) IP GT IP Serial. 3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface XGMII. 1 Throughput 11 2. 25 Mbps. Additionally, for applications requiring 20 Gbps throughput, Intel FPGA's XAUI PHY solution can support DXAUI (4 x 6. © 2012 Lattice Semiconductor Corp. Its work covers 2G/3G/4G/5G. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. 11. 7. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI, DXAUI, RXAUI, 10GBASE-R/KR LogiCORE using the XGMII Interface. Signal. Configuration Registers x. PHY register map Original: PDF P1394a P1394a 32-bit 64-bit 1A16 S100 EIA-364-B: 2004 - Not Available. It came into use in 1999, and has replaced Fast. 1. 4. standard FR-4 material. OpenRAN is a project initiated by the Telecom Infra Project (TIP). The following features are supported in the 64b6xb: Fabric width is selectable. This specification defines USGMII. The XGMII design in the 10-Gig MAC is available from CORE. 25 MHz interface clock. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は必須ではないが、PCSはXGMIIを想定して仕様が定義されて. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. ÐÏ à¡± á> þÿ. Uses device-specific transceivers for the RXAUI interface. It utilizes built-in transceivers to implement the XAUI protocol in a single device. 0. Features 1. (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2. For example, connecting either a 1000BASE-T1 PHY or a 100BASE-T1 PHY to the same RGMII or. The subsidized sponsorship of standards via the IEEE GET Program helps expand the global reach of technical knowledge developed by industry, accelerates adoption of IEEE standards, contributes to an open knowledge community, promulgates open information exchange to foster innovation, and connects the IEEE brand with the development of. Features 6. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. Inter-Packet Gap Generation and Insertion 4. 3ba standard. The XGMII is a low-speed parallel interface for short range (approximately 2”) interconnects. But HSTL has more usage for high speed interface than just XGMII. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. The XGMII is a low-speed parallel interface for short range (approximately 2”) interconnects. The PHY side of the MAC implements the XLGMII or CGMII protocol as defined by the IEEE 802. With experience of SSTL, I believe we can define the HSTL interface in more reasonable time frame. To use custom preamble, set the tx_preamble_control register to 1. This specification, the Devicetree Specification (DTSpec), provides a complete boot program to client program interface definition, combined with minimum system requirements that facilitate the development of a wide variety of systems. • Data Capture: Record data packets in-line between twoThe present clauses in 802. MDI – Media dependant interface. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and. 49. We are using the Yocto Linux SDK. 7. 25 MHz interface clock. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. In this demo, the FiFo_wrapper_top module provides this interface. 2 External interface requirements. Related LinksSublayers (XGXS) to extend the reach of the XGMII for 10 Gb/s operation. This table lists all the Intel ® Arria 10 designs for Low Latency Ethernet 10G MAC Intel FPGA IP. 25 Gbps line rate to achieve 10-Gbps data rate. Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. About the F-Tile 1G/2. 3-2008 clause 48 State Machines. 3 Plenary, HSSG meeting, Atlanta, GA 11 10G Service interfaces XGMII is standardized instantiation of PCS interface (Clause 46) XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interfaceVMDS-10298. 3 81. XGMII electricals > > > > > > >In an effort to get us all on the same page, here are links to >the standard XGMII interface proposals, SSTL-2 and HSTL Class 1 >on the JEDEC site under "Free Standards© 2012 Lattice Semiconductor Corp. O-RAN can. Reconciliation Sublayer (RS) and XGMII. 0 > 2. 3125 Gbps). This is for use within products designed for. 3-2005. 1. Figure 46–1 shows the relationship of the RS and XGMII to the ISO/IEC (IEEE) OSI reference model. PMD. 3-2012 clause 45;Support to extend the IEEE 802. 5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, JESD8-6” (1995年8月1日). XGMII Signals 6. 1. The shared logic is configured to be included in the example design. 2023年11月1日 閲覧。 ^ IEEE 802. Figure 46–1 shows the relationship of the RS and XGMII to the ISO/IEC (IEEE) OSI reference model. 4. 25MHz? I'm currently reading the IEEE XGMII specification (IEEE Std 802. 1. 3. XGMII Signals 6. Xilinx has 10G/25G Ethernet Subsystem IP core. It is primarily used to connect a video source to a display device such as a computer monitor. Actually - I should amend this answer - XGMII isn't the correct protocol, I think I'm thinking of 10GBASE-R. 5. Overview. I see three alternatives that would allow us to go forward to > TF ballot. 2 Predict & Fetch 11. The 10 Gigabit Media Independent Interface ( XGMII) is an interface standard that uses 72 data pins for both RX and TX. 1. 32 Gbps over a copper or optical media interface. 3 Plenary, HSSG meeting, Atlanta, GA 11 10G Service interfaces XGMII is standardized instantiation of PCS interface (Clause 46) XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface10-Gbps Ethernet MAC MegaCore Function user guide ›. Unlike previous Ethernet. The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a Cadence or third-party MAC through a demultiplexed XGMII (64-bit data, 8-bit control, single clock-edge interface). XGMII Signals 6. So to test initially I taken Example design of PCS/PMA IP and there I altered 1) ctl_loopback bit 1-> 0 (not setting in loop back) . the 10 Gigabit Media Independent Interface (XGMII). PHY 8. It cannot have a method body. This document provides the technical specification for the Non-Real-Time RAN Intelligent Controller (Non-RT RIC) architecture. The PHY we have on the LS1046A RDB supports native XFI but sends PAUSE frames towards the MAC to regulate the lower speeds. Low Latency Ethernet 10G MAC 8. FPGA. This guide and its associated documents provide recommendations on the use of the _DSD (Device Specific Data) object as defined in the ACPI Specification . The modules are capable of operating with XGMII interface widths of 32 or 64 bits. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP\+ optical module using SFI electrical specification. So I don't think there's an easy way to connect 100G and 25G. 1. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including: Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. This solution is designed to the IEEE 802. XAUI v12. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device. September 23, 2021 Product Specification Rev1. Network Management. The XgmiiSource drives XGMII traffic into a design. USGMII supports eight 10M/100M/1G network ports over 10Gbps SERDES between MAC and PHY. 2 XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI) Serial Interface Signals 6. 802.